The 19th Workshop on Design and Architectures for Signal and Image Processing
(DASIP 2026) will take place in conjunction with the
HiPEAC 2026 conference
in Kraków, Poland, 26-28 January 2026.
Preliminary Cycle
15 September 2025 → 21 September 2025
Paper submission deadline: 19 September 2025 → 26 September 2025
Notification and feedbacks: sent
Main Cycle
10 November 2025 → 17 November 2025
Paper submission deadline: 17 November 2025 → 24 November 2025
Notification: sent
Camera-ready submission deadline: 17 January 2026
All deadlines are for 23:59 Anywhere on Earth (AoE)
Machine learning and deep learning architectures for inference and training
Systems for autonomous vehicles: cars, drones, ships and space applications
Image processing and compression architectures
Smart cameras, security systems, behaviour recognition
Edge and cloud processing: special routing, configurable coprocessors and low energy
considerations
Real-time cryptography, secure computing, financial and personal data processing
Computer arithmetic, approximate computing, probabilistic computing, nanocomputing, bio-inspired
computing
Biological data collection and analysis, bioinformatics
Personal digital assistants, natural language processing, wearable computing and implantable
devices
Global navigation satellite and inertial navigation systems
Design verification and fault tolerance
Embedded system security and security validation
System-level design and hardware/software co-design
High-level synthesis, logic synthesis, communication synthesis
Embedded real-time systems and real-time operating systems
Rapid system prototyping, performance analysis and estimation
Formal models, transformations, algorithm transformations and metrics
Embedded platforms for multimedia and telecommunication
Many-core and multi-processor systems, SoCs, and NoCs
Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
Memory system and cache management
Asynchronous (self-timed) circuits and analog and mixed-signal circuits
Paweł Skruch is a Professor at the AGH University of Kraków. He graduated in 2001 in Automation and Robotics, obtained his PhD in 2006, and completed his habilitation in 2016. Since 2025, he has held the title of Full Professor in the Department of Automatic Control and Robotics at AGH, where he leads the Dynamic Systems and Control Theory Group. His expertise lies at the intersection of control theory, artificial intelligence, and autonomous systems, with applications in autonomous vehicles, robotics, and advanced driver assistance systems. He has participated in numerous interdisciplinary projects combining engineering, computer science, and applied mathematics, focusing on the design of safe and reliable solutions for modern mobility and intelligent systems. He has led several research projects funded by the European Union and the National Centre for Research and Development in Poland, as well as industry projects in automated driving, whose results have been successfully implemented by global automotive corporations. He actively collaborates with research institutions in Europe, Asia, and the United States.
Title: The Evolution of Automotive System Architectures in the Era of Software-Defined Vehicles
Abstract: The automotive industry is undergoing a profound transformation driven by the transition from hardware-centric designs toward software-defined vehicle (SDV) architectures. This shift fundamentally reshapes how sensing, signal and image processing, decision-making, and control functions are designed, integrated, and deployed within modern vehicles. This keynote traces the evolution of automotive system architectures, from distributed electronic control units (ECUs) with tightly coupled functionalities to centralized and zonal architectures enabled by high-performance computing platforms and software abstraction layers. Particular emphasis is placed on the implications of this evolution for perception systems, where traditional signal- and image-processing pipelines are increasingly replaced or augmented by data-driven and end-to-end learning approaches. The presentation discusses architectural challenges and opportunities arising from SDVs, including sensor fusion, real-time constraints, functional safety, verification and validation, and the coexistence of model-based and learning-based components. Drawing on examples from advanced driver assistance systems and autonomous driving applications, the keynote highlights how architectural decisions influence system performance, scalability, and robustness. The talk concludes by outlining emerging trends and open research directions, positioning software-defined architectures as a key enabler for future intelligent, adaptive, and updatable automotive systems.
Adam Morawiec is a Senior Director at Arteris and General Manager of the Polish subsidiary of this American company. Before joining Arteris he was involved in the European business development of Jasper Design Automation (a formal verification tools company) and lead Evatronix SA (a high-precision 3D scanning and IoT company). He was also a Director at the European Electronic Chips & Systems design Initiative (ECSI) coordinating several European R&D projects, conferences and workshops (including FDL and DASIP). He received his MSc degree from Politechnika Śląska in Gliwice, Poland and the PhD degree from Université Joseph Fourier / INPG / TIMA Laboratory in Grenoble, France.
Title: Network-on-Chip IP for Efficient AI Architectures
Abstract: System-on-Chip (SoC) design complexity has surpassed manual human capabilities, requiring smart interconnect automation based on Network-on-Chips (NoCs). Modern SoCs have 5 to 20+ unique NoC instances and each instance can require 5-10 design iterations in the entire product development. Arteris delivers the data movement IP hardware and IP block integration software to connect in an automated way on-chip components and chiplets. Their use in design process translates to several advantages: efficient and automated on-chip transport organization enables higher performance in terms of data throughput and latency, lower cost related to interconnect complexity and in silicon surface and overall lower power consumption. In addition, chip design productivity can be shortened by the factor up to 10x shortening and reducing iterations from weeks to days. This presentation will provide some insight into these solutions.
Marcin Kowalczyk
AGH University of Kraków
Kraków, Poland
kowalczyk@agh.edu.pl
Camille Monière
Lab-STICC / University Bretagne Sud
Lorient, France
camille.moniere@univ-ubs.fr
João M. P. Cardoso
University of Porto, Portugal
Miguel Chavarrías
Universidad Politécnica de Madrid, Spain
Jean-Pierre David
Ecole Polytechnique de Montreal, Canada
Karol Desnos
INSA Rennes - IETR laboratory, France
Diana Goehringer
TU Dresden, Germany
Marek Gorgoń
AGH University of Krakow, Poland
Michael Huebner
Brandenburg University of Technology, Cottbus-Senftenberg, Germany
Tomasz Kryjak
AGH University of Krakow, Poland
Paolo Meloni
University of Cagliari, Cagliari, Italy
Sergio Pertuz
TU Dresden, Germany
Sebastien Pillement
University of Nantes - IETR, France
Andrea Pinna
Sorbonne University, France
Alfonso Rodríguez
Universidad Politécnica de Madrid, Spain
Gabriel Caffarena
University CEU San Pablo, Spain
Daniel Chillet
IRISA / ENSSAT University of Rennes 1, France
Christopher Claus
Robert Bosch GmbH, Germany
Dominique Dallet
IMS / ENSEIRB-Matmeca Bordeaux-INP, France
Martin Danek
Daiteq s.r.o., Czechia
Eduardo de La Torre
Universidad Politécnica de Madrid, Spain
Milos Drutarovsky
Technical University of Kosice, Slovak Republic
João Canas Ferreira
University of Porto, Portugal
Guy Gogniat
Lab-STICC / University Bretagne Sud, France
Bertrand Granado
Sorbonne Université, France
Oscar Gustafsson
Linköping University, Sweden
Frank Hannig
Friedrich-Alexander University Erlangen-Nürnberg, Germany
Kamil Jeziorek
AGH University of Kraków, Poland
Mateusz Komorkiewicz
IEEE, Poland
Bertrand Le Gal
INRIA / ENSSAT University of Rennes 1, France
Yannick Le Moullec
Tallinn University of Technology, Estonia
Johan Lilius
Åbo Akademi University, Finland
Kevin J. M. Martin
Lab-STICC / University Bretagne-Sud, France
Vincent Migliore
LAAS-CNRS Université de Toulouse, France
Jean Francois Nezan
IETR / INSA Rennes, France
Arnaldo Oliveira
Universidade de Aveiro - DETI / Instituto de Telecomunicações, Portugal
Andrés Otero
Universidad Politécnica de Madrid, Spain
Alessandro Palumbo
INRIA Rennes, France
Francesca Palumbo
Information Eng. Unit - PolComIng - University of Sassari, Italy
Lazaros Papadopoulos
Democritus University of Thrace, Greece
Maxime Pelcat
IETR / INSA Rennes, France
Christian Pilato
Politecnico di Milano, Italy
Jorge Portilla
Universidad Politécnica de Madrid, Spain
Francesco Ratto
Università degli Studi di Cagliari, Italy
Tiago Rocha
INESC-ID Universidade de Lisboa, Portugal
Nuno Roma
Universidade de Lisboa, Portugal
Olivier Romain
University of Cergy Pontoise, France
Claudio Rubattu
University of Sassari, Italy
Ruben Salvador
CentraleSupélec - IETR, France
Hubert Szolc
AGH University of Kraków, Poland
Mateusz Wąsala
AGH University of Kraków, Poland
In conjunction with the 20th HiPEAC Conference
Barcelona, Spain
January 20-21
Website
In conjunction with the 19th HiPEAC Conference
Munich, Germany
January 17-19
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In conjunction with the 18th HiPEAC Conference
Toulouse, France
January 16-18
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In conjunction with the 17th HiPEAC Conference
Budapest, Hungary
June 20-22
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In conjunction with the 16th HiPEAC Conference
Virtual Conference, Online
January 18-20
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Polytechnique Montréal, Canada
October 16-18
Website
University of Porto, Portugal
October 10-12
Website
Technical University of Dresden, Germany
September 27-29
RISA/INRIA Rennes, France
October 12-14
AGH University of Science and Technology, Poland
September 23-25
Technical University of Madrid, Spain
October 8-10
University of Cagliari, Italy
October 8-10
Karlsruhe Institute of Technology, Germany
October 23-25
Tampere University of Technology, Finland
November 2-4
University of Edinburgh, UK
October 26-28
Sophia Antipolis, France
September 22-24
Brussels, Belgium
November 24
Grenoble, France
November 27-29